A new model for voltage output charge-pump phase frequency detector in resonant inverter tuning loops

KILINÇ S., Karaca H.

47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japonya, 25 - 28 Temmuz 2004, ss.301-304 identifier identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Cilt numarası:
  • Basıldığı Şehir: Hiroshima
  • Basıldığı Ülke: Japonya
  • Sayfa Sayıları: ss.301-304
  • Dokuz Eylül Üniversitesi Adresli: Evet

Özet

Resonant inverters mostly employ tuning loops based on a phase-locked-loop (PILL) circuit. Some commercially available PLL chips, frequently used in this application, include a voltage output charge-pump phase frequency detector (CP/PFD) rather than well-known current output CP/PFD, which complicates the analysis of the loop. We present a new model for voltage output CPIPFD and an analysis of a tuning loop, which uses this model. The proposed model employs the resistance multiplication approach, which is applicable for the circuits containing periodically operated switches. It is shown that a voltage output CPIPFD in conjunction with a simple low-pass filter can be modeled using a DC voltage source, a phase error controlled resistor and a filter capacitor for positive phase error (theta) values. For negative theta values DC voltage source is shorted and the sign of the resistance is reversed. The theoretical study is verified by experimental results.